1. Field of the Invention
The present invention relates to a semiconductor nonvolatile memory device for performing page programming in units of word lines such as a NAND type flash memory, more particularly relates to an increase of speed of data programming.
2. Description of the Related Art
In the semiconductor nonvolatile memory device such as a NAND type flash memory and DINOR type flash memory, data programming is carried out together for all memory transistors connected to a selected word line.
Namely, the page programming is carried out in units of word lines.
FIG. 1A and FIG. 1B are views of the structure of a memory array in a NAND type and DINOR type flash memory.
The NAND type flash memory of FIG. 1A is, for convenience, shown as a memory array where four memory transistors are connected to one NAND string connected to one bit line.
In FIG. 1A, BL denotes a bit line. A NAND string in which two selection transistors ST1 and ST2 and four memory transistors MT1 to MT4 are connected in series is connected to the bit line BL.
The selection transistors ST1 and ST2 are respectively controlled by selection gate lines SL1 and SL2, while the memory transistors MT1 to MT4 are respectively controlled by word lines WL1 to WL4.
The DINOR type flash memory of FIG. 1B is, for convenience, shown as a memory array where four memory transistors are connected to one sub-bit line connected to one main bit line.
In FIG. 1B, MBL denotes the main bit line, and SBL denotes the sub-bit line. The main bit line MBL and the sub-bit line SBL are connected via the selection transistor ST1 controlled by the selection gate line SL.
The sub-bit line SBL intersects with four word lines WL1 to WL4. Four memory transistors MT1 to MT4 are arranged at intersection positions.
In a semiconductor nonvolatile memory device for performing page programming in units of word line sectors such as a NAND type and DINOR type flash memory, the programming of the data is carried out as follows.
Namely, data programming is performed by providing a data latch circuit for temporarily latching the page program data for every bit line (or main bit line) and continuously performing two steps, that is, a data transfer step for transferring the page program data to the data latch circuit and a data programming step for performing page programming together for memory transistors connected to the selected word line according to the page programming data.
FIG. 2 shows a timing chart of a semiconductor nonvolatile memory device for performing conventional page programming in units of line sectors, for example, a NAND type flash memory, at the time of data programming.
In FIG. 2, the period from the time t1 to time t3 is a step for performing the first page programming.
First, at the times t1 to t2, the first page program data [Da1]1 to [Da1]m are transferred to the data latch circuit of each bit line in synchronization with a data transfer clock signal .PHI.CL. Here, in the case of a general NAND type flash memory, usually the page size is 512 bytes. Also, the data transfer is carried out in units of bytes, so the number of data transfer clock signal .PHI.CL pulses is generally represented by m=512.
Next, at the times t2 to t3, in synchronization with the data program signal .PHI.PRG, the page programming for the first page program data [Da1]1 to [Da1]m is carried out together for the memory transistors connected to the first selected word line.
Similarly, the term from the times t3 to t5 is a step for performing a second page programming. The page programming is carried out for the second page program data [Da2]1 to [Da2]m together for the memory transistors connected to the second selected word line.
Similarly, the term from the times t5 to t7 is a step for performing a third page programming. The page programming is carried out for the third page program data [Da3]1 to [Da3]m together for the memory transistors connected to the third selected word line.
In the data programming operation of such a conventional NAND type flash memory, the data programming for every page is carried out by dividing the operation into two steps, that is, the data transfer step and the data programming step.
In the case of a general NAND type flash memory, the data transfer clock signal .PHI.CL is driven 512 times by a burst pulse of about 100 nanoseconds, therefore the time required for the data transfer is about 50 microseconds.
On the other hand, in the case of the general NAND type flash memory, the time required for one page worth of the data programming is about 200 microseconds since the data programming is carried out by applying a few pulses of about 40 microseconds.
Accordingly, in the case of a conventional NAND type flash memory, the time required for the transfer of the program data constitutes a remarkably long time with respect to the actual data programming time, so the substantial data programming speed is sacrificed.
Further, along with the increase of the capacity of NAND type flash memories in the future, there is a possibility that the page size will become larger. In this case, it is believed that the actual data programming time and the time required for the transfer of the program data will become almost equal.
Further, in the case of a conventional NAND type flash memory, when the page programming is continuously carried out over a plurality of page areas like when recording for example image information data, it is impossible to transfer a plurality of page program data to the NAND type flash memory in synchronization with continuous burst pulses. It is necessary to divide the data into each page program data for transfer.
In the case of a general NAND type flash memory, the page program data is divided and transferred under the control of an external controller.
Accordingly, there is a problem that the data programming operation cannot be carried out unless under the control of an external controller.